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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:29:20 09/24/2013 
-- Design Name: 
-- Module Name:    add_sub_32 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity add_sub_32 is
    Port ( a : in  STD_LOGIC_VECTOR (31 downto 0);
           b : in  STD_LOGIC_VECTOR (31 downto 0);
           subControl : in STD_LOGIC;
			  sum : out  STD_LOGIC_VECTOR (31 downto 0);
           carryOut : out  STD_LOGIC;
			  isEqual : out STD_LOGIC);
end add_sub_32;

architecture Behavioral of add_sub_32 is
	component adder_32 
		 Port ( a : in  STD_LOGIC_VECTOR (31 downto 0);
				  b : in  STD_LOGIC_VECTOR (31 downto 0);
				  carryIn : in  STD_LOGIC;
				  sum : out  STD_LOGIC_VECTOR (31 downto 0);
				  carryOut : out  STD_LOGIC);
	end component;

	signal bIntermediate : STD_LOGIC_VECTOR(31 downto 0);
	signal carryIn0 : STD_LOGIC := '0';
	signal carryOutIntermediate : STD_LOGIC;
	signal sumIntermediate : STD_LOGIC_VECTOR (31 downto 0);
begin
	adder1 : adder_32 port map(a, bIntermediate, carryIn0, sumIntermediate, carryOutIntermediate);
	
	bIntermediate <= b when subControl = '0' else
							NOT(b);
	
	carryIn0 <= '0' when subControl = '0' else
					'1';
	
	carryOut <= carryOutIntermediate;
	
	sum <= sumIntermediate;
	
	isEqual <= 	'1' when sumIntermediate = X"00000000" and carryOutIntermediate = '1' else
					'0';
end Behavioral;

